As a semiconductor device process moves toward a finer level, for example a nanometer level, even a crystalline defect having size of several tens of nanometers causes reduction in yield of devices. Accordingly, semiconductor device makers increasingly use a wafer having the controlled crystalline defects as a semiconductor substrate.
However, based on Voronkov's theory, a process margin in the manufacture of a defect-free single crystalline ingot is influenced by a vertical temperature gradient of a radial direction, and thus invariably, the temperature gradient should be large and uniform in a radial direction.
According to Voronkov's theory, as shown in FIG. 1, in the case that a V/G value is larger than a critical value due to high speed growth, a vacancy-rich (V-rich) region is formed, which may be resulted from voids. In the case that a V/G value is smaller than a critical value due to low speed growth, an OSF (Oxidation induced Stacking Fault) region is formed near a crystalline. In the case of lower speed growth, an interstitial-rich (I-rich) region is formed that is resulted from a dislocation loop formed by concentration of interstitial silicon. And, a defect-free region that is neither a V-rich region nor an I-rich region is formed between the V-rich region and the I-rich region. The defect-free region includes a Pv region, or a residual vacancy type defect-free region and a Pi region, or a residual interstitial type defect-free region. In V/G, V indicates a pulling speed of a single crystalline ingot and is a convection term of a point defect in the silicon single crystalline. And, G indicates an axial temperature gradient near an interface of a melt and is a diffusion term of a point defect by the temperature gradient in a crystalline.
Generally, in the manufacture of a single crystalline wafer, a margin of a defect-free region is influenced by a temperature gradient of a radial direction, and thus a difference (ΔG) in G value between a center portion of the single crystalline ingot and an edge portion should be small in order to create a uniform temperature gradient in a radial direction.
Conventionally, to manufacture a single crystalline wafer of high margin of a defect-free region, attempts have been made to design a hot zone (HZ) of a heat shield structure located on a solid-liquid interface in various shapes to control a G value of a single crystalline ingot or to adjust a relative location from a maximum heat generation portion of a heater to a surface of a melt to control the convection of a melt or a heat transmission path. And, studies have been made to improve a parameter such as an argon (Ar) flow ratio, a ratio between seed rotation (SR) speed and crucible rotation (CR) speed or types of an electromagnetic field. The related techniques are disclosed in, for example JP Laid-open Patent Publication Nos. 2005-015296, 2006-069803 and 2004-137093.
However, modification to design of a hot zone needs an additional device, and inevitably results in an increase of volume of an equipment, and in the case that a G value of any one of a center portion and an edge portion of a single crystalline ingot is improved, a G value of the other portion is deteriorated. For example, if a bottom of a heat shield structure is designed to be large or thick, the increased degree of a G value of a center portion is trivial in comparison with the increased degree of a G value of an edge portion. As a result, ΔG value is deteriorated.
On the other hand, in the case that an electromagnetic field is improved, change of the electromagnetic field causes change in type of convection of a melt and consequently may reduce a G value or deteriorate ΔG value. And, it is found that a method for optimizing a parameter such as Ar, pressure or SR/CR ratio has a trivial effect.
As shown in FIG. 2(a), a conventional technique for manufacturing a single crystalline ingot of 12 inch diameter and at least 300 kg or 400 kg weight exhibits a narrow process margin due to reduction in a G value of an edge portion, and when manufacturing an Si wafer, causes a DSOD (Direct Surface Oxide Defect) defect (See FIG. 2(b)) in the shape of a ring at a peripheral portion of the wafer, thereby failing to manufacture a defect-free wafer, in which a defect-free margin is uniformly maintained in a radial direction.
And, as disclosed in JP Laid-open Patent Publication No. 2005-015296, in the case that a location of a heater is controlled according to solidification ratio to ensure a margin, an actual growth of a single crystalline ingot involves a latent heat of solidification and changes in G values at a crystalline and a melt due to change in an amount of Si residual melt caused by solidification, from an initial stage of crystallization to the last stage, so that the balance in thermal equilibrium is changed, and a crucible is moved up to maintain a melt level, thereby changing a heat transmission path from the heater to a solid-liquid interface. As such, there is a limitation in maintaining G/ΔG in the lengthwise direction of a crystalline. And, in the case that a charge size is small, for example a single crystalline ingot is grown to 400 kg or 300 kg or less, a latent heat of solidification is relatively small, and thus a pulling speed should be controlled uniformly from an initial stage of growth to the last stage to maintain a margin uniformly, which may reduce productivity.
As an example of the prior art, FIG. 3 shows that as a G value of an edge portion of a single crystalline ingot reduces at the last stage of a single crystalline ingot growth process, a defect-free margin at the last stage remarkably reduces in comparison with a defect-free margin at an initial stage. As mentioned above, this is mainly resulted from a change of latent heat due to change in a residual melt, and reduction in a G value of an edge portion caused by change in the shape of a melt flow and heat transmission due to a hot zone.